About the job
EnCharge AI stands at the forefront of cutting-edge AI hardware and software systems tailored for edge-to-cloud computing. Our advanced in-memory computing technology delivers unparalleled compute efficiency and density, significantly outperforming existing solutions in the market. This high-performance architecture, combined with seamless software integration, unlocks the vast potential of AI, catering to applications that demand power, energy, and space efficiency. Launched in 2022, EnCharge AI is led by experienced technologists with rich backgrounds in semiconductor design and AI systems.
Job Title: Senior Physical Design Engineer
Experience: 4–7 Years
Focus: Block-Level RTL-to-GDSII & PPA Optimization
Location: Bangalore (Hybrid)
The Role
We are seeking a dynamic and technically inquisitive Physical Design Engineer to join our advanced silicon team. This position is not suited for someone who merely follows vendor flows; we need a proactive driver with 4–6 years of hands-on experience in quality tape-outs, eager to take full ownership of complex design partitions.
In this role, you will work with significant independence, utilizing your analytical skills to transform standard processes into world-class PPA results. You should be comfortable following expert guidance while challenging the status quo to identify more efficient solutions.
Key Responsibilities
- Partition Ownership: Lead the physical implementation of complex blocks from Synthesis and Floor-planning through to CTS, Routing, and Sign-off.
- PPA Recipe Development: Optimize the design flow by performing in-depth analysis on timing paths, power profiles, and congestion to derive tailored optimization strategies.
- Automation-First Mindset: Leverage Tcl and Python to automate repetitive tasks, create custom analysis scripts, and enhance the overall efficiency of the physical design environment.
- Independent Convergence: Transition design partitions from

