About the job
At d-Matrix, we are dedicated to unlocking the transformative power of generative AI to revolutionize technology. Positioned at the cutting edge of software and hardware innovation, we strive to redefine the limits of what is achievable. Our workplace is rooted in respect and collaboration.
We prioritize humility and encourage open communication. Our inclusive team values diverse perspectives, which lead to more effective solutions. We are on the lookout for passionate individuals who thrive on challenges and are motivated by results. Are you ready to discover your playground? Together, we can explore the infinite possibilities of AI.
Location:
Hybrid, with onsite work at our Bengaluru, Karnataka headquarters 3-5 days a week.
Position Overview:
d-Matrix is seeking a seasoned DFT Engineer to join our rapidly expanding DFT design team. In this role, you will define, specify, and implement cutting-edge DFX solutions for AI Accelerators SoCs. We are pioneering AI acceleration through Digital In-Memory Computing (DIMC) and advanced chiplet architectures, achieving unmatched efficiency for data centers and large language models (LLMs). As a Series B startup supported by industry leaders, we blend the agility of a disruptor with the technical aspirations of a market frontrunner.
Become part of an energetic team and elevate your career in a challenging and captivating field that is constantly evolving! We can’t wait to welcome you aboard!
Your Responsibilities Will Include:
Partitioning for ATPG and hierarchical approaches
ATPG compression and serialization
RTL-Scan insertion and design rule correction
Expertise in Memory BIST, including Memory Repair and In-System Test (IST) from implementation to verification and silicon debugging
Experience with Boundary Scan and writing DFT mode constraints for IPs, providing timing feedback to the STA team for DFT modes
DFT RTL generation and integration with RTL level QC checks such as Spyglass LINT, Spyglass DFT, and Fishtail
Familiarity with IEEE1149.1, IEEE1500, and IEEE1687 standards
Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations
Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis

