About the job
About Voltai
At Voltai, we are pioneering the development of advanced world models and intelligent agents that learn, evaluate, and interact with the physical environment. Our initial focus lies in understanding and enhancing hardware, particularly in electronics systems and semiconductors, where AI surpasses human cognitive capabilities in design and innovation.
About the Team
Our team is comprised of elite professionals backed by top investors in Silicon Valley, Stanford University, and industry leaders including CEOs and Presidents from Google, AMD, Broadcom, and Marvell. We bring together former Stanford professors, SAIL researchers, Olympiad medalists, and high-ranking officials from the U. S. government, all working collaboratively towards groundbreaking advancements.
Mid-Level Training Opportunity
In this role, you will play a crucial part in training cutting-edge models to become experts in semiconductor design and verification, laying the groundwork for reinforcement learning and automated chip development. You will innovate methods for generating and curating synthetic design data, executing model distillation, and facilitating scalable continual learning. Collaboration will be key, as you will partner with hardware engineers, reinforcement learning researchers, and verification specialists to optimize design data quality and enhance model performance. You will also work alongside compute engineers to efficiently scale training across thousands of GPUs and RL environments, developing high-performance tools to analyze how data and simulations influence model-driven design intelligence.
Ideal Candidates Will Have Experience In:
Training large language models or foundation models on semiconductor design and verification datasets (e.g., RTL, netlists, PDKs, simulation logs)
Modeling design scaling laws and optimizing compute budgets for chip-design-specific tasks
Generating extensive synthetic design data (e.g., RTL variations, testbenches, verification traces)
Developing evaluations that correlate with downstream design metrics (e.g., timing closure, power efficiency, area, verification coverage)
