About the job
At Tenstorrent, we are at the forefront of AI technology, transforming the landscape of performance expectations, user-friendliness, and cost-effectiveness. As AI reshapes computing paradigms, our solutions are designed to integrate innovations across software models, compilers, platforms, networking, and semiconductors. Our talented team has successfully built a high-performance RISC-V CPU from the ground up, fueled by our passion for AI and a relentless pursuit of excellence in creating the best AI platform. We foster a collaborative environment that values curiosity and a strong commitment to overcoming complex challenges. We are expanding our team and invite professionals of all experience levels to join us.
In the role of Staff Design for Test STA Engineer, you will serve as a pivotal technical leader responsible for ensuring the testability, quality, and performance of our cutting-edge AI processors. This position demands an in-depth understanding of Design for Test (DFT) architecture and implementation, along with extensive expertise in Static Timing Analysis (STA) for intricate SoCs. Your responsibilities will include defining and executing the comprehensive DFT methodology for our high-speed, multi-core designs, overseeing top-level timing constraints and sign-offs for all DFT modes, and collaborating closely with RTL, Physical Design, and Product Engineering teams to ensure the successful first-pass silicon production.
This position follows a hybrid work model, with opportunities available in either Santa Clara, CA, or Austin, TX.
We welcome candidates from various experience levels for this opportunity. During the interview process, applicants will be evaluated based on their qualifications, and offers will be made accordingly, which may differ from the details specified in this posting.
