About the job
At Tenstorrent, we are at the forefront of pioneering AI technology, challenging the norms of performance, usability, and cost-effectiveness. As AI reshapes the landscape of computing, we are committed to evolving our solutions to integrate advancements in software models, compilers, platforms, networking, and semiconductor technologies. Our dynamic team has successfully built a high-performance RISC-V CPU from the ground up, fueled by a collective passion for AI and a relentless drive to create the ultimate AI platform. We cherish collaboration, curiosity, and a strong commitment to tackling complex challenges. As we expand our team, we welcome contributors across all experience levels.
We are currently on the lookout for a Physical Design Engineer to take charge of timing for subsystems within our AI accelerator chip. In this role, you will work closely with RTL designers during the design exploration phase to evaluate the feasibility and performance, power, and area (PPA) of micro-architectural features. Your tasks will involve developing timing constraints and guiding the transition to physical design implementation. Key responsibilities include synthesis, place and route, timing analysis and closure, and power optimization. With a wide design space available for AI accelerators, your contributions will be crucial in selecting micro-architecture design points that align with die-size and PPA objectives.
This position offers a hybrid work environment, with options based in Austin, TX, Santa Clara, CA, or Fort Collins, CO.
We invite candidates of all experience levels to apply. During the interview process, we will assess each candidate's fit for the appropriate level, and compensation will correspond accordingly, which may differ from the level indicated in this posting.
