About the role
Normal Computing | Exceptional Career Opportunities
At Normal Computing, we are pioneers in developing cutting-edge software and hardware solutions that propel technology into the future. Our contributions are vital to the semiconductor sector, essential AI infrastructure, and the expansive frameworks that sustain our world. Our collaborative team spans across New York, San Francisco, Copenhagen, Seoul, and London.
Your Role in Our Vision:
Join us as we construct an AI accelerator from scratch, where your expertise as a machine learning compiler engineer will play a pivotal role in hardware-software co-design. This position is not about working with an established compiler stack; it’s about forging a new one.
You will engage at the architecture definition phase, significantly impacting the Instruction Set Architecture (ISA) design and the critical trade-offs that dictate our hardware’s capabilities. As we advance towards hardware bring-up, your task will involve developing a comprehensive compiler toolchain that translates machine learning models from high-level frameworks into efficient execution on our innovative architecture.
This unique opportunity allows you to simultaneously influence both silicon and software. Collaborate with hardware architects and researchers to co-design compiler strategies that maximize the potential of our accelerator, building infrastructure that connects machine learning model graphs with custom ISA primitives. Your decisions on the compiler will directly affect hardware features, and the capabilities of the hardware will open new optimization pathways for your toolchain.
If you are passionate about architecting a compiler stack from the ground up, optimizing machine learning workloads on novel hardware, and witnessing your decisions come to life in silicon, we want to hear from you.
Key Responsibilities:
Collaborate with software, systems, and hardware teams to ensure correctness, performance, and deployment readiness for real-world workloads.
Contribute to defining the long-term compiler architecture and tooling strategy in a dynamic startup atmosphere.
Design and implement components of the compiler stack tailored for our AI accelerator, including front-end lowering, intermediate representation transformations, optimization passes, and backend code generation.
Develop and enhance MLIR/LLVM-based infrastructure to facilitate graph lowering, hardware-aware optimizations, and performance-focused code emission.
Work closely with hardware architects, microarchitects, and research teams to co-design compiler strategies that adapt to evolving ISA and hardware requirements.
Create profiling and analysis tools to identify performance bottlenecks, validate generated code, and ensure high-quality output.
